Integrated circuit memory devices typically include address inputs for receiving address signals to identify a memory location which is to be accessed for storing or retrieving data. The received address signals are decoded and used to access memory cell locations. In conventional memory devices, memory cells are accessed through access, or isolation Transistors. These Transistors are activated by a signal provided on a "wordline" coupled to a gate of the Transistor. As such, the signal on the wordline must remain valid while the memory cell is accessed. Because the wordline signal is typically generated using the address signals, if the address signals are changed during an access operation, memory data read or write operations may be prematurely interrupted resulting in a memory operation error.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which latches a wordline signal to maintain access to memory locations while allowing externally provided address signals to change. In particular, memory devices which contain multiple banks of memory cells and share common address inputs will experience faster data access by allowing address signal changes to occur for a first memory bank while simultaneously maintaining access to a second memory bank.